May 11 2015
Xilinx, Inc. and its ecosystem will demonstrate next generation vision technologies at the Embedded Vision Summit 2015. Xilinx® All Programmable technologies drive advances in embedded vision systems and neural networks acceleration. Learn more about the Embedded Vision Summit and register today at: http://www.embedded-vision.com/summit.
Xilinx Participation at Embedded Vision Summit 2015
Xilinx Conference Presentation
"Implementing Eye Tracking for Medical, Automotive and Headset Applications"
Tuesday, May 12, 2015, 11 a.m. – 12 p.m., Santa Clara Convention Center
Presented by Robert Chappell, CEO, EyeTech Digital Systems, and Dan Isaacs, Director of Smart Connected Systems, Xilinx
Xilinx In-Booth Demonstrations
- Accelerating Canny Edge Detection in a Pure Software Environment by iVeia: This demonstration will showcase iVeia's canny edge detect implemented in two ways: running the algorithm on the processor only, and accelerating the algorithm using Xilinx's software development environment, SDSoC, without running any low level code.
- Deep Learning Convolutional Neural Network Acceleration at Lower Power by TeraDeep: This demonstration will highlight more than 20X power reduction running Deep Learning software in FPGAs (5 Watts) compared with CPU (>100 Watts).
- Medical Development Platform by Topic Embedded Systems: This demonstration will illustrate how easily different video filters can be built into software and accelerated in hardware, leveraging the Zynq® All Programmable SoC with Dyplo software running on the Miami System on Module (SoM) from Xilinx Premier Alliance Member Topic Embedded Systems.
- Compact Eye Tracking System by EyeTech: This demonstration will showcase an intelligent eye tracking camera that uses the Zynq All Programmable SoC for all of its image processing.
Demonstrations by Xilinx Alliance Program Members
- Auviz Systems Accelerated OpenCL-based Convolutional Neural Network Demonstration: Xilinx Alliance Member Auviz Systems will demonstrate AlexNet running on a Xilinx Virtex®-7 FPGA. AlexNet is a Convolutional Neural Network built using Auviz's OpenCL library and implemented with Xilinx's SDAccel environment.
- Avnet Face Detection and Tracking and GigE Vision Demonstration: Xilinx Alliance Member Avnet will be demonstrating a face detection and tracking application developed by Premier Alliance Member Xylon on the Avnet MicroZed Embedded Vision Development Kit. The real-time demonstration finds and tracks the face and facial features in video sequences and returns full 3D head pose, gaze direction, facial features coordinates, and a wealth of other information. Also demonstrated is a GigE Vision application developed by Alliance Member Sensor to Image on the Avnet PicoZed Smarter Vision Development Kit.
- Inrevium/Fidus Development Solutions for Embedded Vision and Video Demonstration: Xilinx Certified Alliance Member inrevium and Premier Alliance Member Fidus demonstrate board and IP products with customization services that jump-start embedded vision development. Technologies showcased are Kintex® UltraScale™ FPGA and Artix®-7 FPGA 4K/8K development platforms, paired with HDMI4K, MIPI, and 12G-SDI interconnect solutions, along with DisplayPort, eDP, VbyOne, and video gearboxes.
- MathWorks Rapid People Detector Implementation for Zynq Using Simulink HDL Coder Demonstration: Xilinx Alliance Member MathWorks demonstrates Model-Based Design for rapid co-design and prototyping of a sophisticated vision system that accelerates people detection using the HOG algorithm on the Zynq All Programmable SoC. The design is modeled and verified in MATLAB and Simulink, then partitioned and accelerated on Zynq.
- National Instruments USB 3.0 and GigE Vision based Embedded Vision Demonstration: Xilinx Alliance Program Member National Instruments demonstrates LabVIEW real-time/FPGA vision programming tool chain for embedded vision applications on both Zynq All Programmable SoC based sbRIO-9651 System on Module (SoM) with USB 3.0 and CVS-1458RT Real-Time Compact Vision System for GigE Vision Cameras leveraging a Spartan-6 FPGA for I/O, vision co-processing, and customization.