New Pixel-Streaming Algorithms for Design of Vision Systems on FPGAs and ASICs from MathWorks

MathWorks today introduced Vision HDL Toolbox, a new product now available in the company’s Release 2015a. Vision HDL Toolbox provides pixel-streaming algorithms for the design and implementation of vision systems on FPGAs and ASICs.

The toolbox also includes a design framework that supports a diverse set of interface types, frame sizes, and frame rates, including high-definition (1080p) video. The image processing, video, and computer vision algorithms in the toolbox use an architecture appropriate for HDL implementations.

Vision algorithm developers are challenged by the combination of increasing video frame sizes, frame rates, and the complexity of prototyping or implementing the vision algorithms on FPGA and ASIC platforms. Vision HDL Toolbox helps developers overcome these challenges by providing a library of image processing and computer vision algorithms specifically designed for FPGA and ASIC implementation, as well as automatic conversion between frames of various sizes and pixels. In addition, when used with HDL Coder, designers can generate readable and vendor-independent HDL code from these algorithms. And, with HDL Verifier, designers can connect the algorithms running on the FPGA or ASIC with frame-based test models running in MATLAB or Simulink.

“FPGAs in particular are an increasingly popular platform for image processing and computer vision systems,” said John Zhao, marketing manager at MathWorks. “The new Vision HDL Toolbox has been created to help developers prototype and implement systems faster, with shortened design cycles, and more efficiently, through the ability to identify design errors early in the workflow and minimize the time needed for writing HDL code.”

Key Vision HDL Toolbox Features

• Image processing, video, and computer vision algorithms with a pixel-streaming architecture, including image enhancement, filtering, morphology, and statistics
• Frame-to-pixel and pixel-to-frame conversions to integrate with frame-based processing capabilities in MATLAB and Simulink
• Video synchronization signals for handling nonideal timing and resolution variations
• Configurable frame rates and frame sizes, including 60FPS for high-definition (1080p) video
• Support for HDL code generation and real-time verification

For pricing and more information, see Vision HDL Toolbox. This product is available immediately worldwide.