Efabless Corporation: Second AI Generated Open-Source Silicon Design Challenge Launched

Efabless Corporation, the creator platform for chips, announces the launch of its second in a series of AI Generated Open-Source Silicon Design Challenges. In the first design challenge, several participants successfully submitted completed designs in just three weeks. The second challenge will extend the design time to two months to enable wider participation, more learnings, and more success. The challenge series is targeted at a broad range of participants including IC designers, university students, professors, industry experts, and even those who have never designed a chip.

A lot has been written about the rapid emergence of generative AI in chip design. Large Language Model (LLM) AI is widely acknowledged as being an important productivity tool, with questions raised about its limitations. The Efabless AI Generated Open-Source Silicon Design Challenge series engages a global community in LLM AI chip creation to demonstrate the state of the art over time. The use of open source and an open forum enables and encourages broad based sharing of solutions and experiences across the community, accelerating its development and adoption.

As with the first challenge in the series, contestants will use AI tools to generate Verilog code from natural language prompts, which they will then implement on the Efabless chipIgnite platform using the OpenLane open-source design flow.

The deadline for submissions is September 7, 2023. A panel of industry experts will select the top three designs and announce the winners on September 14, 2023. Efabless will once again fabricate the winning designs and award the winners packaged silicon devices incorporating their designs along with evaluation boards, amounting to a total value of $9,750.

"We are excited to launch the second AI Generated Open-Source Silicon Design Challenge," said Mike Wishart, CEO of Efabless. "Our inaugural contest showcased the incredible potential of AI in shaping the future of chip design, and we cannot wait to witness the exceptional ideas that will emerge this time around."

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